Synopsys Passes PCI Express

Synopsys, Inc. (NASDAQ:SNPS) , a software and IP for semiconductor design and manufacturing vendor, today announced that its DesignWare(R) digital controller and PHY IP for the PCI Express(R) 2.0 technology is the first complete, single-vendor PCI Express 2.0 IP solution to successfully pass the PCI Express 2.0 compliance testing at the PCI-Special Interest Group (PCI-SIG(R)) workshop held in Taiwan in October 2008. Passing PCI Express 2.0 compliance testing helps ensure interoperability while reducing risk and time-to-market for designers incorporating the complex, high-performance interface. As the only IP vendor to offer a complete, silicon-proven and compliant PCI Express 2.0 solution consisting of digital controllers, PHYs and Verification IP, Synopsys continues to demonstrate industry leadership.

The PCI Express 2.0 specification doubles the 1.1 specification transfer speed from 2.5 Gbps to 5.0 Gbps per lane, helping to meet the demand for increased bandwidth in data center, servers, networking and storage applications. Backward compatibility with PCI Express 1.1 allows designers to increase performance, while maintaining interoperability with existing devices.

The DesignWare digital controllers for PCI Express 2.0 fully support the PIPE interface standard and the PCI-SIG I/O Virtualization (IOV) suite of specifications. Synopsys offers digital controllers for Endpoint, Root Complex, Switch and Bridge applications. In addition, designers implementing the ARM AMBA(R) 3 AXI(TM) and AMBA AHB(TM) on-chip interconnect can easily add PCI Express 2.0 functionality to their SoC designs by using either the DesignWare Bridge IP for PCI Express to AMBA 3 AXI or AMBA AHB.

"The enhanced performance available with the PCI Express 2.0 interconnect standard helps address the increased bandwidth requirements in next-generation enterprise computing infrastructure applications," said Al Yanes, PCI-SIG chairman and president. "We are happy to see that Synopsys, an active member of PCI-SIG, continues to support the PCI Express standard in the market by providing IP solutions that enable designer to integrate the PCI Express interface into their products."
The DesignWare PHY IP substantially exceeds key PCI Express 2.0 specifications in the areas of jitter, margin and receive sensitivity thus delivering a robust design that tolerates process, voltage and temperature variations. Embedded high-speed mixed signal IP, such as a PCI Express 2.0 PHY, can pose significant testing challenges in terms of development time, coverage and equipment cost. With the DesignWare PHY for PCI Express, at-speed production testing can be conducted on a pure digital tester by using the supplied ATE test vectors for full compliance eye-mask testing. This eliminates the need for expensive test equipment, enabling designers to speed development time and lower costs. Furthermore, the advanced built-in diagnostics capabilities provide customers with an on-chip sampling scope for quick debug of the SoC.

The DesignWare Verification IP for PCI Express 2.0 supports directed testing and the constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog. To help designers test the integration of the DesignWare digital controller IP in their SoC designs, the DesignWare Verification IP is included with the DesignWare digital controller for PCI Express 2.0.

"As a leader in PCI Express IP, Synopsys has hundreds of design wins with our DesignWare PCI Express solutions, and our customers are shipping PCI Express 2.0-based designs in high volume production today," said John Koeter, vice president of marketing, Synopsys Solutions Group. "Achieving compliance for our complete IP solution enables designers to lower interoperability risks and speed time to market for their PCI Express products."

Synopsys Intel Certification

Synopsys, Inc. (NASDAQ:SNPS) , a vendor of software and IP for semiconductor design and manufacturing, today announced that Synopsys' DesignWare(R) IP for PCI Express(R) with PCI-SIG(R) I/O Virtualization (IOV) technology has completed testing at Intel's labs and will be used as the gold standard to demonstrate single root IOV (SR-IOV) running on the latest Intel hardware platforms at next week's Intel Developer Forum (IDF).

The silicon-proven DesignWare digital controller and PHY IP for PCI Express with PCI-SIG IOV technology has been thoroughly tested using Intel's SR-IOV hardware platforms and Independent Hardware Vendor (IHV) test software, demonstrating that the IP is interoperable and functions in accordance to the PCI-SIG IOV specification. Proven interoperability of the DesignWare IP for PCI Express allows designers to lower the risk of integrating PCI-SIG IOV technology into their system-on-chips (SoCs) and helps speed adoption of the standard.

"Demonstrating interoperability between the DesignWare IP for PCI Express with Intel's hardware platform is an example of how Synopsys continues to actively promote and support the latest industry standards," said John Koeter, Vice President of Marketing for IP and Services at Synopsys. "As a leader in PCI Express IP, we provide proven, interoperable and high quality IP for SR- IOV, which helps designers quickly deliver differentiated blades, servers and storage systems to the market."

"SR-IOV is a key technology that is being driven for enterprise computing customers to lower costs and increase performance of virtualized systems," said Jim Pappas, Director of Initiative Marketing for Intel Corporation. "By working closely with leading technology companies such as Synopsys, Intel is contributing to an ecosystem that consists of the latest tools, IP and platforms that support the PCI-SIG IOV technology."