MoSys, Inc., a Silicon Valley provider of high-density system-on-chip (SoC) memory intellectual property (IP), has selected Adventests's T5781 Engineering Station (T5781ES), for design and debug of its next generation embedded memory technologies. MoSys' products incorporate its patented technologies -- 1T-SRAM (based on a dynamic bit cell, which uses a single transistor and capacitor and achieves a considerable size advantage) and 1T-FLASH IP (a cost-effective, higher-performance alternative to conventional embedded non-volatile memory) -- which are widely used in advanced SoCs found in mobile devices, home entertainment, networking and storage applications. MoSys selected Advantest's T5781ES for its compact size, its unique FutureSuite(R) software tools and its ability to characterize new device technologies at speeds up to 500MHz.
The T5781ES is the laboratory complement to Advantest's T5781 high-speed, high-throughput memory test system for Flash and MCPs, devices which combine multiple memory types -- such as NAND, NOR and DRAM -- in a single package. The T5781ES integrates all of the functions and performance of the T5781 into a very compact footprint that offers low cost test program development and device evaluation and analysis. The system's FutureSuite software maximizes the functionality and engineering tools of the per-site architecture, delivering multi-language program development and device evaluation and analysis from design through production.
"The adoption of Advantest's T5781ES will enable MoSys to greatly enhance our test and characterization capability for our high-speed memory IP, allowing us to provide our customers with the extremely high performance and high quality memory IP that they require to ensure the success of their SoCs. Advantest's reputation for cost-effective, quality test capabilities precedes it, and we are confident that the selection of the T5781ES will enable MoSys to continue to offer its global customers products that are both industry-leading and highly reliable," commented Hem Hingarh, VP of Engineering of MoSys, Inc. "Furthermore, FutureSuite's powerful device characterization tools will allow MoSys to evaluate and examine deep engineering aspects of our newest technologies and improve our time to market," he continued.
"We are very proud that MoSys has chosen Advantest to serve as a test partner to their next-generation technology," said Greg Self, executive vice president at Advantest America, Inc. "We are excited for the opportunity to work with this esteemed company and to provide them with the benchmark testing capabilities and time to market advantages that will help them drive their business forward."
Showing posts with label semiconductor testing. Show all posts
Showing posts with label semiconductor testing. Show all posts
Thursday, 26 February 2009
Wednesday, 7 January 2009
Synopsys Passes PCI Express
Synopsys, Inc. (NASDAQ:SNPS) , a software and IP for semiconductor design and manufacturing vendor, today announced that its DesignWare(R) digital controller and PHY IP for the PCI Express(R) 2.0 technology is the first complete, single-vendor PCI Express 2.0 IP solution to successfully pass the PCI Express 2.0 compliance testing at the PCI-Special Interest Group (PCI-SIG(R)) workshop held in Taiwan in October 2008. Passing PCI Express 2.0 compliance testing helps ensure interoperability while reducing risk and time-to-market for designers incorporating the complex, high-performance interface. As the only IP vendor to offer a complete, silicon-proven and compliant PCI Express 2.0 solution consisting of digital controllers, PHYs and Verification IP, Synopsys continues to demonstrate industry leadership.
The PCI Express 2.0 specification doubles the 1.1 specification transfer speed from 2.5 Gbps to 5.0 Gbps per lane, helping to meet the demand for increased bandwidth in data center, servers, networking and storage applications. Backward compatibility with PCI Express 1.1 allows designers to increase performance, while maintaining interoperability with existing devices.
The DesignWare digital controllers for PCI Express 2.0 fully support the PIPE interface standard and the PCI-SIG I/O Virtualization (IOV) suite of specifications. Synopsys offers digital controllers for Endpoint, Root Complex, Switch and Bridge applications. In addition, designers implementing the ARM AMBA(R) 3 AXI(TM) and AMBA AHB(TM) on-chip interconnect can easily add PCI Express 2.0 functionality to their SoC designs by using either the DesignWare Bridge IP for PCI Express to AMBA 3 AXI or AMBA AHB.
"The enhanced performance available with the PCI Express 2.0 interconnect standard helps address the increased bandwidth requirements in next-generation enterprise computing infrastructure applications," said Al Yanes, PCI-SIG chairman and president. "We are happy to see that Synopsys, an active member of PCI-SIG, continues to support the PCI Express standard in the market by providing IP solutions that enable designer to integrate the PCI Express interface into their products."
The DesignWare PHY IP substantially exceeds key PCI Express 2.0 specifications in the areas of jitter, margin and receive sensitivity thus delivering a robust design that tolerates process, voltage and temperature variations. Embedded high-speed mixed signal IP, such as a PCI Express 2.0 PHY, can pose significant testing challenges in terms of development time, coverage and equipment cost. With the DesignWare PHY for PCI Express, at-speed production testing can be conducted on a pure digital tester by using the supplied ATE test vectors for full compliance eye-mask testing. This eliminates the need for expensive test equipment, enabling designers to speed development time and lower costs. Furthermore, the advanced built-in diagnostics capabilities provide customers with an on-chip sampling scope for quick debug of the SoC.
The DesignWare Verification IP for PCI Express 2.0 supports directed testing and the constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog. To help designers test the integration of the DesignWare digital controller IP in their SoC designs, the DesignWare Verification IP is included with the DesignWare digital controller for PCI Express 2.0.
"As a leader in PCI Express IP, Synopsys has hundreds of design wins with our DesignWare PCI Express solutions, and our customers are shipping PCI Express 2.0-based designs in high volume production today," said John Koeter, vice president of marketing, Synopsys Solutions Group. "Achieving compliance for our complete IP solution enables designers to lower interoperability risks and speed time to market for their PCI Express products."
The PCI Express 2.0 specification doubles the 1.1 specification transfer speed from 2.5 Gbps to 5.0 Gbps per lane, helping to meet the demand for increased bandwidth in data center, servers, networking and storage applications. Backward compatibility with PCI Express 1.1 allows designers to increase performance, while maintaining interoperability with existing devices.
The DesignWare digital controllers for PCI Express 2.0 fully support the PIPE interface standard and the PCI-SIG I/O Virtualization (IOV) suite of specifications. Synopsys offers digital controllers for Endpoint, Root Complex, Switch and Bridge applications. In addition, designers implementing the ARM AMBA(R) 3 AXI(TM) and AMBA AHB(TM) on-chip interconnect can easily add PCI Express 2.0 functionality to their SoC designs by using either the DesignWare Bridge IP for PCI Express to AMBA 3 AXI or AMBA AHB.
"The enhanced performance available with the PCI Express 2.0 interconnect standard helps address the increased bandwidth requirements in next-generation enterprise computing infrastructure applications," said Al Yanes, PCI-SIG chairman and president. "We are happy to see that Synopsys, an active member of PCI-SIG, continues to support the PCI Express standard in the market by providing IP solutions that enable designer to integrate the PCI Express interface into their products."
The DesignWare PHY IP substantially exceeds key PCI Express 2.0 specifications in the areas of jitter, margin and receive sensitivity thus delivering a robust design that tolerates process, voltage and temperature variations. Embedded high-speed mixed signal IP, such as a PCI Express 2.0 PHY, can pose significant testing challenges in terms of development time, coverage and equipment cost. With the DesignWare PHY for PCI Express, at-speed production testing can be conducted on a pure digital tester by using the supplied ATE test vectors for full compliance eye-mask testing. This eliminates the need for expensive test equipment, enabling designers to speed development time and lower costs. Furthermore, the advanced built-in diagnostics capabilities provide customers with an on-chip sampling scope for quick debug of the SoC.
The DesignWare Verification IP for PCI Express 2.0 supports directed testing and the constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog. To help designers test the integration of the DesignWare digital controller IP in their SoC designs, the DesignWare Verification IP is included with the DesignWare digital controller for PCI Express 2.0.
"As a leader in PCI Express IP, Synopsys has hundreds of design wins with our DesignWare PCI Express solutions, and our customers are shipping PCI Express 2.0-based designs in high volume production today," said John Koeter, vice president of marketing, Synopsys Solutions Group. "Achieving compliance for our complete IP solution enables designers to lower interoperability risks and speed time to market for their PCI Express products."
Aehr Test Systems 2009 Q2 Results
Aehr Test Systems (NASDAQ:AEHR) , a supplier of semiconductor test and burn-in equipment, today announced financial results for the second quarter of fiscal 2009 ended November 30, 2008.
Net sales were $9.2 million in the second quarter of fiscal 2009, compared with $9.7 million in the second quarter of fiscal 2008. Pre-tax income was $1.6 million in the second quarter of fiscal 2009, compared with $1.6 million in the second quarter of fiscal 2008. Aehr Test reported net income of $872,000, or $0.10 per diluted share, in the second quarter of fiscal 2009, compared with net income of $1.4 million, or $0.16 per diluted share, in the second quarter of fiscal 2008. Net income for the second quarter of fiscal 2009 reflects a significantly higher effective tax rate than the same period of the prior year, as the Company now expects to accrue tax expense at close to the statutory rates for the countries in which it generates income.
"Our net sales for the second quarter of fiscal 2009 came in lower than we originally expected, as we saw customers delay new orders or defer delivery on existing orders in light of the current economic slowdown," said Rhea Posedel, chairman and chief executive officer of Aehr Test Systems. "During this slowdown we are focusing on two strategies. First, we hope to maintain our strong financial position by maximizing our cash balance and keeping expenses low. In response to the challenging business conditions, we implemented a two-week shutdown of our facilities in December, and are actively exploring other measures to control or reduce our expenses until capital spending in the semiconductor equipment industry returns to more normal levels. Second, we are aggressively introducing new products, such as our ABTS system, which are targeting new test and burn-in market segments. We believe that our aggressive product development and marketing efforts during this time will position us well to win additional business with new and existing customers as the semiconductor industry begins to recover."
Net sales were $18.9 million in the first six months of fiscal 2009, an increase of 9% when compared with $17.3 million in the first six months of fiscal 2008. Net income for the six months ended November 30, 2008 was $1.7 million, or $0.20 per diluted share, compared with net income of $2.1 million, or $0.26 per diluted share, in the same period of the prior fiscal year.
At November 30, 2008, cash and cash equivalents and short-term investments were $13.7 million, an increase of $4.3 million from the balance at the end of the prior quarter. Aehr Test closed the second quarter of fiscal 2009 with no outstanding debt and shareholders' equity of $40.8 million, or $4.83 per share outstanding, at November 30, 2008.
Commenting on the outlook for Aehr Test Systems, Gary Larson, vice president and chief financial officer, said, "We are not expecting a meaningful improvement in this difficult operating environment until the second half of calendar 2009 at the earliest. Accordingly, due to the uncertainties in our market, we find it imprudent to provide guidance for the next several quarters."
Net sales were $9.2 million in the second quarter of fiscal 2009, compared with $9.7 million in the second quarter of fiscal 2008. Pre-tax income was $1.6 million in the second quarter of fiscal 2009, compared with $1.6 million in the second quarter of fiscal 2008. Aehr Test reported net income of $872,000, or $0.10 per diluted share, in the second quarter of fiscal 2009, compared with net income of $1.4 million, or $0.16 per diluted share, in the second quarter of fiscal 2008. Net income for the second quarter of fiscal 2009 reflects a significantly higher effective tax rate than the same period of the prior year, as the Company now expects to accrue tax expense at close to the statutory rates for the countries in which it generates income.
"Our net sales for the second quarter of fiscal 2009 came in lower than we originally expected, as we saw customers delay new orders or defer delivery on existing orders in light of the current economic slowdown," said Rhea Posedel, chairman and chief executive officer of Aehr Test Systems. "During this slowdown we are focusing on two strategies. First, we hope to maintain our strong financial position by maximizing our cash balance and keeping expenses low. In response to the challenging business conditions, we implemented a two-week shutdown of our facilities in December, and are actively exploring other measures to control or reduce our expenses until capital spending in the semiconductor equipment industry returns to more normal levels. Second, we are aggressively introducing new products, such as our ABTS system, which are targeting new test and burn-in market segments. We believe that our aggressive product development and marketing efforts during this time will position us well to win additional business with new and existing customers as the semiconductor industry begins to recover."
Net sales were $18.9 million in the first six months of fiscal 2009, an increase of 9% when compared with $17.3 million in the first six months of fiscal 2008. Net income for the six months ended November 30, 2008 was $1.7 million, or $0.20 per diluted share, compared with net income of $2.1 million, or $0.26 per diluted share, in the same period of the prior fiscal year.
At November 30, 2008, cash and cash equivalents and short-term investments were $13.7 million, an increase of $4.3 million from the balance at the end of the prior quarter. Aehr Test closed the second quarter of fiscal 2009 with no outstanding debt and shareholders' equity of $40.8 million, or $4.83 per share outstanding, at November 30, 2008.
Commenting on the outlook for Aehr Test Systems, Gary Larson, vice president and chief financial officer, said, "We are not expecting a meaningful improvement in this difficult operating environment until the second half of calendar 2009 at the earliest. Accordingly, due to the uncertainties in our market, we find it imprudent to provide guidance for the next several quarters."
Tuesday, 6 January 2009
Aehr Test Contract
Aehr Test Systems (NASDAQ:AEHR) , a supplier of semiconductor test and burn-in equipment, today announced it has received a second order for their new Advanced Burn-in and Test System (ABTS) from a leading European provider of imbedded wireless technology. The system is configured for burning-in and testing advanced logic devices.
"The technology in the ABTS is based on our successful FOX(TM)-1 full-wafer contact burn-in and test system," said Greg Perkins, vice president of worldwide sales and service at Aehr Test Systems. "Although numerous FOX systems are currently in high volume production in many parts of the world this will be the first version of the ABTS package part burn-in and test system shipped to Europe. Other members of the ABTS family will focus on high-power logic and memory devices."
The ABTS family of products is based on a completely new hardware and software architecture that is designed to address not only today's devices, but also future devices for many years to come. It can test and burn-in memory as well as both high-power logic and low-power logic. It can be configured to provide individual device temperature control for devices up to 50W or more and with up to 320 I/O channels. It uses N+1 redundancy technology for many key components in the system to provide the highest possible system uptime.
"The technology in the ABTS is based on our successful FOX(TM)-1 full-wafer contact burn-in and test system," said Greg Perkins, vice president of worldwide sales and service at Aehr Test Systems. "Although numerous FOX systems are currently in high volume production in many parts of the world this will be the first version of the ABTS package part burn-in and test system shipped to Europe. Other members of the ABTS family will focus on high-power logic and memory devices."
The ABTS family of products is based on a completely new hardware and software architecture that is designed to address not only today's devices, but also future devices for many years to come. It can test and burn-in memory as well as both high-power logic and low-power logic. It can be configured to provide individual device temperature control for devices up to 50W or more and with up to 320 I/O channels. It uses N+1 redundancy technology for many key components in the system to provide the highest possible system uptime.
Thursday, 6 November 2008
InTest 2008 Q3 Results
inTEST Corporation (NASDAQ:INTT) , an independent designer, manufacturer and marketer of semiconductor automatic test equipment (ATE) interface solutions and temperature management products, today announced results for the quarter ended September 30, 2008.
Net revenues for the quarter ended September 30, 2008 were $9.2 million, compared to $11.5 million in the second quarter of 2008. Our net loss for the third quarter of 2008 was $(2.0) million or $(0.22) per diluted share, compared to a net loss of $(1.4) million or $(0.15) per diluted share for the second quarter of 2008. The net loss for the third quarter of 2008 included charges for impairment of long-lived assets of $133,000 or $0.01 per diluted share and restructuring charges of $61,000 or $0.01 per diluted share, while the net loss for the second quarter of 2008 included restructuring charges of $200,000 or $.02 per diluted share. The impairment of long-lived assets is related to the planned closure of our Amerang, Germany manufacturing facility which was previously announced and the restructuring charges are the result of one-time termination benefits related to our workforce reductions.
Robert E. Matthiessen, President and Chief Executive Officer of inTEST commented, "the continuing weakness and turmoil of the macroeconomic environment has caused a significant reduction in capital spending in the semiconductor industry. This, in turn, has resulted in a decrease in our bookings in the third quarter to $8.2 million, compared to $10.0 million in the second quarter of 2008. With that in mind, we have implemented further restructuring to right-size our operations to the anticipated revenue levels of the foreseeable future. This effort will result in additional restructuring costs in the fourth quarter of 2008. On the positive side, we have begun the integration of Sigma Systems Corporation which we acquired on October 6, 2008.
Sigma is a manufacturer of thermal platforms, custom configured environmental chambers and other environmental test solutions. Sigma will be joining inTEST in a strategic fit with Temptronic that will greatly expand our product offerings outside the semiconductor market, including the automotive, medical/pharmaceutical, electronic, and aerospace/defense markets. We expect that this expansion of our business into markets outside of semiconductor capital equipment will greatly enhance our pursuit of profitability in the future."
Net revenues for the quarter ended September 30, 2008 were $9.2 million, compared to $11.5 million in the second quarter of 2008. Our net loss for the third quarter of 2008 was $(2.0) million or $(0.22) per diluted share, compared to a net loss of $(1.4) million or $(0.15) per diluted share for the second quarter of 2008. The net loss for the third quarter of 2008 included charges for impairment of long-lived assets of $133,000 or $0.01 per diluted share and restructuring charges of $61,000 or $0.01 per diluted share, while the net loss for the second quarter of 2008 included restructuring charges of $200,000 or $.02 per diluted share. The impairment of long-lived assets is related to the planned closure of our Amerang, Germany manufacturing facility which was previously announced and the restructuring charges are the result of one-time termination benefits related to our workforce reductions.
Robert E. Matthiessen, President and Chief Executive Officer of inTEST commented, "the continuing weakness and turmoil of the macroeconomic environment has caused a significant reduction in capital spending in the semiconductor industry. This, in turn, has resulted in a decrease in our bookings in the third quarter to $8.2 million, compared to $10.0 million in the second quarter of 2008. With that in mind, we have implemented further restructuring to right-size our operations to the anticipated revenue levels of the foreseeable future. This effort will result in additional restructuring costs in the fourth quarter of 2008. On the positive side, we have begun the integration of Sigma Systems Corporation which we acquired on October 6, 2008.
Sigma is a manufacturer of thermal platforms, custom configured environmental chambers and other environmental test solutions. Sigma will be joining inTEST in a strategic fit with Temptronic that will greatly expand our product offerings outside the semiconductor market, including the automotive, medical/pharmaceutical, electronic, and aerospace/defense markets. We expect that this expansion of our business into markets outside of semiconductor capital equipment will greatly enhance our pursuit of profitability in the future."
Thursday, 14 August 2008
Synopsys Intel Certification
Synopsys, Inc. (NASDAQ:SNPS) , a vendor of software and IP for semiconductor design and manufacturing, today announced that Synopsys' DesignWare(R) IP for PCI Express(R) with PCI-SIG(R) I/O Virtualization (IOV) technology has completed testing at Intel's labs and will be used as the gold standard to demonstrate single root IOV (SR-IOV) running on the latest Intel hardware platforms at next week's Intel Developer Forum (IDF).
The silicon-proven DesignWare digital controller and PHY IP for PCI Express with PCI-SIG IOV technology has been thoroughly tested using Intel's SR-IOV hardware platforms and Independent Hardware Vendor (IHV) test software, demonstrating that the IP is interoperable and functions in accordance to the PCI-SIG IOV specification. Proven interoperability of the DesignWare IP for PCI Express allows designers to lower the risk of integrating PCI-SIG IOV technology into their system-on-chips (SoCs) and helps speed adoption of the standard.
"Demonstrating interoperability between the DesignWare IP for PCI Express with Intel's hardware platform is an example of how Synopsys continues to actively promote and support the latest industry standards," said John Koeter, Vice President of Marketing for IP and Services at Synopsys. "As a leader in PCI Express IP, we provide proven, interoperable and high quality IP for SR- IOV, which helps designers quickly deliver differentiated blades, servers and storage systems to the market."
"SR-IOV is a key technology that is being driven for enterprise computing customers to lower costs and increase performance of virtualized systems," said Jim Pappas, Director of Initiative Marketing for Intel Corporation. "By working closely with leading technology companies such as Synopsys, Intel is contributing to an ecosystem that consists of the latest tools, IP and platforms that support the PCI-SIG IOV technology."
The silicon-proven DesignWare digital controller and PHY IP for PCI Express with PCI-SIG IOV technology has been thoroughly tested using Intel's SR-IOV hardware platforms and Independent Hardware Vendor (IHV) test software, demonstrating that the IP is interoperable and functions in accordance to the PCI-SIG IOV specification. Proven interoperability of the DesignWare IP for PCI Express allows designers to lower the risk of integrating PCI-SIG IOV technology into their system-on-chips (SoCs) and helps speed adoption of the standard.
"Demonstrating interoperability between the DesignWare IP for PCI Express with Intel's hardware platform is an example of how Synopsys continues to actively promote and support the latest industry standards," said John Koeter, Vice President of Marketing for IP and Services at Synopsys. "As a leader in PCI Express IP, we provide proven, interoperable and high quality IP for SR- IOV, which helps designers quickly deliver differentiated blades, servers and storage systems to the market."
"SR-IOV is a key technology that is being driven for enterprise computing customers to lower costs and increase performance of virtualized systems," said Jim Pappas, Director of Initiative Marketing for Intel Corporation. "By working closely with leading technology companies such as Synopsys, Intel is contributing to an ecosystem that consists of the latest tools, IP and platforms that support the PCI-SIG IOV technology."
Wednesday, 13 August 2008
inTEST Q2 Results
inTEST Corporation (NASDAQ:INTT) , an independent designer, manufacturer and marketer of semiconductor automatic test equipment (ATE) interface solutions and temperature management products, today announced results for the quarter ended June 30, 2008.
Net revenues for the quarter ended June 30, 2008 were $11.5 million, compared to $11.3 million in the first quarter of 2008. Our net loss for the second quarter of 2008 was $(1.4) million or $(0.15) per diluted share, compared to a net loss of $(1.3) million or $(0.14) per diluted share for the first quarter of 2008.
Robert E. Matthiessen, President and Chief Executive Officer of inTEST commented, "The weakening of the macroeconomic environment in the second quarter posed significant challenges to our overall profitability and growth. Bookings decreased in the second quarter of 2008 to $10.0 million, compared to $12.5 million in the first quarter of 2008. Our negative results for the second quarter were driven by the Manipulator and Docking Hardware product segment. At the end of the second quarter we implemented a restructuring of this product segment and reduced headcount by 18% and shortened the workweek for certain employees. We will continue to concentrate on this segment's cost structure, new product releases and sales efforts during the third quarter of 2008."
Net revenues for the quarter ended June 30, 2008 were $11.5 million, compared to $11.3 million in the first quarter of 2008. Our net loss for the second quarter of 2008 was $(1.4) million or $(0.15) per diluted share, compared to a net loss of $(1.3) million or $(0.14) per diluted share for the first quarter of 2008.
Robert E. Matthiessen, President and Chief Executive Officer of inTEST commented, "The weakening of the macroeconomic environment in the second quarter posed significant challenges to our overall profitability and growth. Bookings decreased in the second quarter of 2008 to $10.0 million, compared to $12.5 million in the first quarter of 2008. Our negative results for the second quarter were driven by the Manipulator and Docking Hardware product segment. At the end of the second quarter we implemented a restructuring of this product segment and reduced headcount by 18% and shortened the workweek for certain employees. We will continue to concentrate on this segment's cost structure, new product releases and sales efforts during the third quarter of 2008."
Sunday, 22 June 2008
Advantest Nvidia Order
Advantest Corporation , the world's leading supplier of semiconductor test equipment, announces that NVIDIA Corporation (NASDAQ:NVDA) , the world leader in visual computing technologies, has placed a multi-system purchase order for Advantest's T2000 open-architecture SoC Test System. The systems will be used on NVIDIA's products to support parallel testing of their high-pincount, leading-edge graphics devices. NVIDIA made its initial investment in the T2000 in 2006 for characterization and debug of packaged silicon products. Shipments against this latest order will begin immediately and will continue throughout the calendar year.
Advantest reports that NVIDIA selected the T2000 test solution for its cost effectiveness and ability to meet the ongoing complex test requirements of its leading-edge graphics processors. The T2000's parallel test capabilities and unique modular design offer an unprecedented degree of flexibility and extendibility for future-generations of devices, including the ability to incorporate new modules specifically designed to support application-specific requirements.
"We are extremely pleased to be expanding our relationship with NVIDIA and grateful for the high level of confidence they have placed in our ability to respond to their needs. Advantest is committed to serving NVIDIA through our global support team, and to helping them grow their share of the competitive graphics and computing applications market," commented R. Keith Lee, president and CEO of Advantest America, Inc. "In this era of elaborate visual computing, NVIDIA's innovative products continue to drive and define the worldwide market. We are gratified that the cost-efficient and very reliable T2000 has been selected to test these high-performance devices," Lee continued.
Keith Katcher, NVIDIA's Vice President of Operations for Silicon Engineering, remarked, "Advantest continues to demonstrate that their leading-edge technology and test systems have the capabilities necessary to help NVIDIA achieve the highest levels of performance and cost efficiencies. We have confidence that Advantest can ably serve our needs as a test partner."
Advantest reports that NVIDIA selected the T2000 test solution for its cost effectiveness and ability to meet the ongoing complex test requirements of its leading-edge graphics processors. The T2000's parallel test capabilities and unique modular design offer an unprecedented degree of flexibility and extendibility for future-generations of devices, including the ability to incorporate new modules specifically designed to support application-specific requirements.
"We are extremely pleased to be expanding our relationship with NVIDIA and grateful for the high level of confidence they have placed in our ability to respond to their needs. Advantest is committed to serving NVIDIA through our global support team, and to helping them grow their share of the competitive graphics and computing applications market," commented R. Keith Lee, president and CEO of Advantest America, Inc. "In this era of elaborate visual computing, NVIDIA's innovative products continue to drive and define the worldwide market. We are gratified that the cost-efficient and very reliable T2000 has been selected to test these high-performance devices," Lee continued.
Keith Katcher, NVIDIA's Vice President of Operations for Silicon Engineering, remarked, "Advantest continues to demonstrate that their leading-edge technology and test systems have the capabilities necessary to help NVIDIA achieve the highest levels of performance and cost efficiencies. We have confidence that Advantest can ably serve our needs as a test partner."
Monday, 26 May 2008
LogicVision Dragonfly Test Platform Launched
LogicVision, Inc. (NASDAQ:LGVN) , a provider of semiconductor built-in-self-test (BIST) and diagnostic solutions, today announced that it is introducing Dragonfly Test Platform(TM), the next generation of its test and diagnostic solutions. The new platform represents LogicVision's most advanced and comprehensive product portfolio. The Dragonfly Test Platform delivers the industry's most effective combination of test quality of results, ease-of-adoption, and test cost reductions specifically targeted for 65nm and 45nm system-on-chip (SoC) designs. Dragonfly also delivers new silicon diagnostics and characterization capabilities that accelerate yield ramps and enable same-day turnaround of silicon from the fab to known-good first sample shipments. The Dragonfly Test Platform will be showcased at the Design Automation Conference being held in Anaheim, California, June 9th through 12th.
"The IC market is under intense profit pressures, resulting in an increased emphasis on reducing all cost components. Reduction in cost per function is driving higher gate density, driving the growth of 65nm and 45nm design starts," said James T. Healy, President and CEO of LogicVision. "The new Dragonfly Test Platform will provide our customers with the key test, silicon bring-up and yield-ramp capabilities they need to meet rapidly increasing cost, quality, and schedule pressures."
"The IC market is under intense profit pressures, resulting in an increased emphasis on reducing all cost components. Reduction in cost per function is driving higher gate density, driving the growth of 65nm and 45nm design starts," said James T. Healy, President and CEO of LogicVision. "The new Dragonfly Test Platform will provide our customers with the key test, silicon bring-up and yield-ramp capabilities they need to meet rapidly increasing cost, quality, and schedule pressures."
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